1. Field of the Invention
The present invention relates to a microphone unit having an electret capacitor formed in a semiconductor substrate.
2. Description of the Background Art
FIG. 5 shows a circuit diagram of a conventional microphone unit MU2. The microphone unit MU2 has an electret capacitor EC. When the electret capacitor EC receives a sound pressure, its capacitance value varies, and an input signal Vin is generated between both electrodes. Thereby, a voice information is reflected in the input signal Vin. An impedance conversion circuit comprising diodes D1 and D2, resistor R1, and N channel MOS transistors T1 and T2, is connected to both terminals of the electret capacitor EC. Specifically, the anode and cathode of the diode D1 are connected to first and second electrodes of the electret capacitor EC, respectively. The anode and cathode of the diode D2 are connected, in the reverse manner of the diode D1, to both terminals of the electret capacitor EC. The resistor R1 is connected in parallel with both terminals of the electret capacitor EC. The source and gate of the transistor T1 are connected to the second and first electrodes of the electret capacitor EC, respectively. The source of the transistor T2 is connected to the drain of the transistor T1. A power supply potential Vdd and a fixed potential Vref1 are applied to the drain and gate of the transistor T2, respectively. A ground potential GND is applied to each back gate of the transistors T1 and T2. A ground potential GND is also applied to the second electrode of the electret capacitor EC.
When no input signal Vin is applied, the voltage between the gate and source of the transistor T1 is maintained at 0 (V), by the diodes D1 and D2, and the resistor R1. With a sound pressure, the capacitance value of the electret capacitor EC varies, and an input signal Vin is generated, thereby the voltage between the gate and source of the transistor T1 varies. Upon this, the current passing between the drain and source varies. Since the transistor T1 is a depletion type, current passes between the drain and source even when the voltage between the gate and source is 0 (V). Due to variations in the current passing between the drain and source of the transistor T1, the current passing between the drain and source of the transistor T2 varies, and the voltage between the gate and source of the transistor T2 varies accordingly. The potential variation in the source of the transistor T2 generates an output signal Vout. The phase of the output signal Vout is the reverse of that of the input signal Vin. As the value of the input signal Vin decreases, the value of the output signal Vout increases. As the value of the input signal Vin increases, the value of the output signal Vout decreases.
FIG. 6 shows an example of the structure of an electret capacitor EC. The electret capacitor EC has, as a first electrode, a wiring film IL2 disposed above a semiconductor substrate SB. The wiring film IL2 is formed above the semiconductor substrate SB, with insulating films IF1 and IF2 interposed. The electret capacitor EC also has, a second electrode, an electret film EL composed of a dielectric to which a certain amount of electrostatic charge is fixed semipermanently. The electret film EL is disposed above the semiconductor substrate SB and spaced apart from the wiring film IL2. The electret film EL is an oscillating film that oscillates with a sound pressure. In FIG. 6, a ground potential GND is applied to the electret film EL.
The semiconductor substrate SB is, for example, a silicon substrate. In FIG. 6, the semiconductor substrate SB contains, for example, a P type impurity. A ground potential GND is applied to the semiconductor substrate SB. A wiring film IL5 serving as wiring on the circuit is disposed on an insulating film IF1, and an insulating film IF2 is formed so as to cover the insulating film IF1 and the wiring film IL5. The insulating films IF1 and IF2 are, for example, an oxide film or nitride film, and the wiring films 112 and IL5 are, for example, a conductive film composed of Al, or the like. An insulative protecting film PF is formed on the upper surface of the wiring film IL2 and insulating film IF2, so as to cover these films. The protecting film PF is also, for example, an oxide film or nitride film.
The diodes D1 and D2, the resistor R1, and the transistors T1 and T2, which are all shown in FIG. 5, but not shown in FIG. 6, are formed in the vicinity of the electret capacitor EC in the semiconductor substrate SB.
In the electret capacitor EC of the structure shown in FIG. 6, a parasitic capacitance will occur between the semiconductor substrate SB and wiring film IL2, because the wiring film IL2 serving as the second electrode is formed in the surface of the semiconductor substrate SB. In FIG. 5, such a parasitic capacitance is represented by “CX”. Since the ground potential GND is applied to the semiconductor substrate SB that is a first electrode of the parasitic capacitor CX, the first electrode of the parasitic capacitor CX has the same potential as the electret film EL. Accordingly, the parasitic capacitor CX is connected in parallel with the electret capacitor EC.
A parasitic capacitor will occur even between the gate and source of the transistor T1. In FIG. 5, such a parasitic capacitor is represented by “CG”.
In the absence of the above-mentioned parasitic capacitors CX and CG, the voltage between the gate and source of the transistor T1, i.e., an input signal Vin, is derived as follows:Vin=Q/Ce where Ce is the capacitance value of the electret capacitor EC, and Q is the electric charge amount of a fixed amount of electrostatic charge held by the electret film EL.
For the case of Ce=1.0 (pF), the input signal Vin is Q/(1.0×10−12) (V).
When the existence of parasitic capacitors CX and CG is taken into consideration, the voltage Vin between the gate and source of the transistor T1 is derived as follows:Vin=Q/(Ce+Cx+Cg)where Cx is the capacitance value of the parasitic capacitor CX, and Cg is the capacitance value of a parasitic capacitor CG.
Letting the capacitance value Ce be the same value as described above, and letting the sum of the capacitance values Cx and Cg be Cx+Cg=9.0 (pF), the input signal Vin results in Q/(10.0×10−12) (V). Thus, in the existence of the parasitic capacitors CX and CG, the value of the input signal Vin is one tenth of that in the absence of the parasitic capacitors CX and CG, thereby weakening the signal to be input between the gate and source of the transistor T1.
That is, by the presence of the parasitic capacitors CX and CG, the value of an input signal Vin is reduced and thus less susceptible to variation, thereby lowering the sensitivity of a microphone unit.